AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Features
Single chip USB 3.0 to 10/100/1000M Gigabit
Ethernet controller with Energy Efficient
Ethernet (EEE) base on digital signal processing
(DSP) technology with low dissipation
USB Device Controller
Integrates on-chip USB 3.0 PHY and
controller compliant to USB Spec 3.0, 2.0 and
1.1
Supports all USB 3.0 power saving modes (U0,
U1, U2, and U3)
Supports USB Super/High/Full Speed modes
with Bus-power or Self-power device
auto-detect capability
High performance packet transfer rate over
USB bus using proprietary burst transfer
mechanism (US Patent Approval)
Gigabit Ethernet Controller
Supports IEEE 802.3az (Energy Efficient
Ethernet)
IEEE 802.3, 802.3u, and 802.3ab compatible
Integrates
10/100/1000Mbps
Gigabit
Ethernet MAC/PHY
Supports dynamic cable length detection and
dynamic power adjustment Green Ethernet
(Gigabit mode only)
Supports parallel detection and automatic
polarity correction
Supports crossover detection and autocorrection
Supports IPv4/IPv6 packet Checksum
Offload Engine (COE) to reduce CPU
loading,
including
IPv4
IP/TCP/UDP/ICMP/IGMP
&
IPv6
TCP/UDP/ICMPv6 checksum check &
generation
Supports TCP Large Send Offload V1
Supports full duplex operation with IEEE
802.3x flow control and half duplex
operation with back-pressure flow control.
Supports IEEE 802.1P Layer 2 Priority
Encoding and Decoding
Supports IEEE 802.1Q VLAN tagging and
2 VLAN ID filtering; received VLAN Tag (4
bytes) can be stripped off or preserved
Supports Jumbo frame
PHY loop-back diagnostic capability
Document No: AX88179/V1.21/06/05/14
Support Wake-on-LAN Function
Supports suspend mode and remote wakeup
via link-change, Magic Packet, Microsoft
wakeup frame and external wakeup pin
Supports Bonjour wake-on-demand
Advanced Power Management Features
Supports power management offload (ARP &
NS)
Supports dynamic power management to
reduce power dissipation during idle or light
traffic
Supports AutoDetach power saving.
Soft-disconnected from USB host when
Ethernet cable is unplugged
Supports advanced link down power saving
during Ethernet cable is unplugged
Supports optional serial EEPROM (93c56/66)
for storing USB Descriptors, Node-ID, etc
Supports embedded eFuse (64-byte) to store
USB Device Descriptors, Node-ID, etc. to save
external EEPROM
Supports automatic loading of USB Device
Descriptors, Node-ID, etc. from embedded
eFuse or external EEPROM after power-on
initialization
Single 25MHz clock input from either crystal or
oscillator source
Integrates on-chip power-on reset circuit
Integrates pipelined RISC (System on a Chip,
SoC) for handling protocol and control functions
68-pin QFN 8mm x 8mm RoHS/REACH
compliant package
Operating over 0°C to 70°C temperature range
Target Applications
USB Dongle
Docking Station
USB Port Replicator
Network Printer
POS, Card Reader
UMPC, MID, Netbook
Ultrabook
Game Console
IP STB, IP TV
Embedded system
ASIX ELECTRONICS CORPORATION
4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsin-Chu City, Taiwan, R.O.C. 300
TEL: 886-3-579-9500
FAX: 886-3-579-9558
Released Date: 06/05/2014
http://www.asix.com.tw/
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Typical System Block Diagrams
Hosted by USB to operate with internal Ethernet PHY only
Figure 1
: USB 3.0 to LAN Adaptor
1
Copyright © 2011-2014 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Copyright © 2011-2014 ASIX Electronics Corporation. All rights reserved.
DISCLAIMER
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical,
including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX may make
changes to the product specifications and descriptions in this document at any time, without notice.
ASIX provides this document “as is” without warranty of any kind, either expressed or implied, including without
limitation warranties of merchantability, fitness for a particular purpose, and non-infringement.
Designers must not rely on the absence or characteristics of any features or registers marked “reserved”, “undefined” or
“NC”. ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before starting a
design of ASIX products.
TRADEMARKS
ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the property of
their respective owners.
2
Copyright © 2011-2014 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Table of Contents
1
2
3
4
INTRODUCTION ....................................................................................................................................................... 6
1.1
GENERAL DESCRIPTION .......................................................................................................................................... 6
1.2
BLOCK DIAGRAM ................................................................................................................................................... 6
1.3
PINOUT DIAGRAM ................................................................................................................................................... 7
SIGNAL DESCRIPTION ........................................................................................................................................... 8
2.1
68-PIN PINOUT DESCRIPTION .................................................................................................................................. 8
2.2
HARDWARE SETTING FOR OPERATION MODE AND MULTI-FUNCTION PINS ......................................................... 10
FUNCTION DESCRIPTION ................................................................................................................................... 11
3.1
USB CORE AND INTERFACES ................................................................................................................................ 11
3.2
ENERGY EFFICIENT ETHERNET (EEE) .................................................................................................................. 11
3.3
10/100/1000M ETHERNET PHY ........................................................................................................................... 11
3.4
GMAC CORE ....................................................................................................................................................... 12
3.5
CHECKSUM OFFLOAD ENGINE (COE)................................................................................................................... 12
3.6
MEMORY ARBITER ............................................................................................................................................... 12
3.7
USB TO ETHERNET BRIDGE .................................................................................................................................. 13
3.8
EFUSE AND CONTROL ........................................................................................................................................... 13
3.9
SEEPROM LOADER INTERFACE .......................................................................................................................... 13
3.10
GENERAL PURPOSE I/O AND LED ........................................................................................................................ 13
3.11
PLL CLOCK GENERATOR ..................................................................................................................................... 14
3.12
RESET GENERATION ............................................................................................................................................. 15
SERIAL EEPROM/EFUSE MEMORY MAP ........................................................................................................ 16
4.1
4.1.1
Node ID (00~02h) ........................................................................................................................................ 18
4.1.2
Flag (EEPROM: 05h, eFuse:18h) ............................................................................................................... 18
4.1.3
Max. Power for Self/Bus Power (07h) ......................................................................................................... 19
4.1.4
EndPoint1 for SS/HS/FS (EEPROM:08h, eFuse: 06h) ................................................................................ 19
4.1.5
Max. Burst for EP3/EP2 (EEPROM: 3Ch, eFuse: 17h) .............................................................................. 19
4.1.6
LED Mode (EEPROM: 42h, eFuse: 19h~1Ah) ............................................................................................ 20
4.1.7
Fixed_pattern (EEPROM: 41~3Dh, eFuse: 1F~1Ah) ................................................................................. 21
4.2
5
DETAILED DESCRIPTION ....................................................................................................................................... 18
INTERNAL ROM DEFAULT SETTINGS ................................................................................................................... 22
4.2.1
Internal ROM Description ........................................................................................................................... 23
4.2.2
External EEPROM Description ................................................................................................................... 25
USB CONFIGURATION STRUCTURE ................................................................................................................ 26
3
Copyright © 2011-2014 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6
5.1
USB CONFIGURATION .......................................................................................................................................... 26
5.2
USB INTERFACE ................................................................................................................................................... 26
5.3
USB ENDPOINTS................................................................................................................................................... 26
ELECTRICAL SPECIFICATIONS ........................................................................................................................ 27
6.1
7
DC CHARACTERISTICS ......................................................................................................................................... 27
6.1.1
Absolute Maximum Ratings ......................................................................................................................... 27
6.1.2
Recommended Operating Condition ............................................................................................................ 27
6.1.3
Leakage Current and Capacitance .............................................................................................................. 28
6.1.4
DC Characteristics of 3.3V I/O Pins ........................................................................................................... 28
6.2
THERMAL CHARACTERISTICS ............................................................................................................................... 28
6.3
POWER CONSUMPTION ......................................................................................................................................... 29
6.4
POWER-UP SEQUENCE .......................................................................................................................................... 30
6.5
AC TIMING CHARACTERISTICS ............................................................................................................................. 31
6.5.1
Clock Timing ................................................................................................................................................ 31
6.5.2
Reset Timing ................................................................................................................................................ 31
6.5.3
Serial EEPROM Timing ............................................................................................................................... 32
PACKAGE INFORMATION ................................................................................................................................... 33
7.1
68-PIN QFN 8X8 PACKAGE ................................................................................................................................... 33
7.2
RECOMMENDED PCB FOOTPRINT FOR 68-PIN QFN 8X8 PACKAGE ....................................................................... 34
8
ORDERING INFORMATION ................................................................................................................................. 35
9
REVISION HISTORY .............................................................................................................................................. 36
APPENDIX A. DEFAULT WAKE-ON-LAN (DWOL) READY MODE..................................................................... 37
4
Copyright © 2011-2014 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
List of Figures
FIGURE 1
: USB 3.0 TO LAN ADAPTOR ............................................................................................................................. 1
FIGURE 2
: BLOCK DIAGRAM ............................................................................................................................................. 6
FIGURE 3
: PINOUT DIAGRAM ............................................................................................................................................. 7
FIGURE 4
: 25MHZ CRYSTAL REFERENCE CIRCUIT .......................................................................................................... 14
List of Tables
TABLE 1
: PINOUT DESCRIPTION ....................................................................................................................................... 9
TABLE 2
: MFA_3 ~ MFA_0 PIN CONFIGURATION .......................................................................................................... 10
TABLE 3
: THE EXTERNAL 25MHZ CRYSTAL UNITS SPECIFICATIONS ............................................................................. 14
TABLE 4
: SERIAL EEPROM MEMORY MAP ................................................................................................................... 16
TABLE 5
: EFUSE (64-BYTE) MEMORY MAP .................................................................................................................... 17
TABLE 6
: LED MODE SETTING TABLE ........................................................................................................................... 21
TABLE 7
: INTERNAL ROM MEMORY MAP ..................................................................................................................... 22
TABLE 8
: INTERNAL ROM DESCRIPTION ....................................................................................................................... 23
TABLE 9
: POWER CONSUMPTION .................................................................................................................................... 29
TABLE 10
: REMOTE WAKEUP TRUTH TABLE ............................................................................................................... 38
5
Copyright © 2011-2014 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
1 Introduction
1.1 General Description
The AX88179 USB 3.0 to 10/100/1000M Gigabit Ethernet controller is a high performance and highly integrated ASIC
which enables low cost, small form factor, and simple plug-and-play Gigabit Ethernet network connection capability for
desktops, notebook PC’s, Ultrabook’s, docking stations, game consoles, digital-home appliances, and any embedded
system using a standard USB port.
The AX88179 features a USB interface to communicate with a USB Host Controller and is compliant with USB
specification V3.0, V2.0, and V1.1. It implements a 10/100/1000Mbps Ethernet LAN function based on IEEE802.3,
IEEE802.3u, and IEEE802.3ab standards with embedded SRAMs for packet buffering. And, it also integrates an on-chip
10/100/1000Mbps EEE-compliant Ethernet PHY to simplify system design.
1.2 Block Diagram
Figure 2
: Block Diagram
6
Copyright © 2011-2014 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
1.3 Pinout Diagram
TEST_N2
GND12A_RX
VCC33IO
XTL25P
XTL25N
GND
EXTWAKE_N
CK25_OUT
VCC3IO
TEST_N3
VCCK
TEST_X
RSET_BG
VCC12A_X
VCC33A_X
CK25_IN
TEST_N4
68-pin QFN package
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
TEST_N5 52
34 SSRX+
MDIP0 53
33 GND12A_RX
MDIN0 54
32 SSRX-
VCC12A 55
31 VCC12A_RX
MDIP1 56
30 GND12A_TX
MDIN1 57
29 SSTX+
VCC33A_G 58
28 GND12A_TX
AX88179
MDIP2 59
27 SSTX-
MDIN2 60
26 VCC12A_TX
VCC12A 61
25 VCC33A
MDIP3 62
24 D-
MDIN3 63
23 D+
TEST_N6 64
22 GND33A
VCCK 65
21 VBUS
TEST0 66
20 SELF_PWR
TEST1 67
19 VCCK
Figure 3
EECK
EECS
EEDIO
MFA_0
MFA_1
10 11 12 13 14 15 16 17
VCC3IO
GPIO_0/PME
9
TEST_N1
GPIO_1
8
VCCK
GPIO_3
7
GNDK
6
MFA_2
5
MFA_3
3 4
GPIO_2
2
TCLK_1
18 RESET_N
1
TCLK_0
TCLK_EN 68
: Pinout Diagram
7
Copyright © 2011-2014 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
2 Signal Description
The following abbreviations apply to the following pin description table.
I12 Input, 1.2V
AI
Analog Input
I3
Input, 3.3V
AO Analog Output
I5
Input, 3.3V with 5V tolerant
AB Analog Bi-directional I/O
O3
Output, 3.3V
PU
Internal Pull Up (75K ohm)
B5
Bi-directional I/O, 3.3V with 5V tolerant
PD
Internal Pull Down (75K ohm)
B3
Bi-directional I/O, 3.3V
S
Schmitt Trigger
P
Power/GND
T
Tri-stateable
2.1 68-pin Pinout Description
Pin Name
D+
DSSTX+
SSTXSSRX+
SSRXVBUS
Type
AB
AB
AB
AB
AB
AB
I5/PD/S
RSET_BG
AO
MDIP0
MDIN0
AB
AB
MDIP1
MDIN1
AB
AB
MDIP2
MDIN2
AB
AB
MDIP3
MDIN3
AB
AB
XTL25P
XTL25N
CK25_OUT
I3
O3
O3
CK25_IN
I3
EECK
B5/PD/T
EECS
B5/PD/T
Pin No
Pin Description
USB Interface
23
USB 2.0 data positive pin.
24
USB 2.0 data negative pin.
29
USB 3.0 transmit data positive pin.
27
USB 3.0 transmit data negative pin.
34
USB 3.0 receive data positive pin.
32
USB 3.0 receive data negative pin.
21
VBUS pin input. Please connect to USB bus power.
Gigabit EEE Ethernet PHY Interface
47
For Ethernet PHY’s internal biasing. Please connect to GND through a
2.49Kohm ±1% resistor.
53
In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/pair, and is the transmit pair in 10Base-T and 100Base-TX.
54
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the
receive pair in 10Base-T and 100Base-TX.
56
In MDI mode, this is the second pair in 1000Base-T, i.e. the BI_DB+/pair, and is the receive pair in 10Base-T and 100Base-TX.
57
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the
transmit pair in 10Base-T and 100Base-TX.
59
In MDI mode, this is the third pair in 1000Base-T, i.e., the BI_DC+/pair.
60
In MDI crossover mode, this pair acts as the BI_DD+/- pair.
62
In MDI mode, this is the fourth pair in 1000Base-T, i.e., the BI_DD+/pair.
63
In MDI crossover mode, this pair acts as the BI_DC+/- pair.
Clock Pins
38
25Mhz ± 0.005% crystal or oscillator clock input.
39
25Mhz crystal or oscillator clock output.
42
A controllable 25Mhz clock output. Please connect it to CK25_IN pin
with a 22 Ohm termination resistor near to CK25_OUT pin.
50
25Mhz clock input. Please connect it to CK25_OUT pin with a 22
Ohm termination resistor.
Serial EEPROM Interface
16
EEPROM Clock. EECK is an output clock to EEPROM to provide
timing reference for the transfer of EECS, and EEDIO signals. EECK
only drive high / low when access EEPROM otherwise keep at tri-state
and internal pull-down.
17
EEPROM Chip Select. EECS is asserted high synchronously with
respect to rising edge of EECK as chip select signal. EECS only drive
high / low when access EEPROM otherwise keep at tri-state and
internal pull-down.
8
Copyright © 2011-2014 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
EEDIO
B5/PU/T
RESET_N
I5/PU/S
EXTWAKE_N
I3/PU/S
SELF_PWR
I5/PD/S
GPIO_3
GPIO_2
GPIO_1
GPIO_0/PME
B3/PD
B3/PD
B3/PD
B3/PD
MFA_3
B3
MFA_2
B3
MFA_1
B3
MFA_0
B3
TCLK_EN
TCLK_0
TCLK_1
TEST0
TEST1
TEST_X
TEST_N1, 2, 3,
4, 5, 6
VCC33A
GND33A
VCC12A_TX
GND12A_TX
VCC12A_RX
GND12A_RX
VCC12A_X
VCC33A_X
VCC12A
VCC33A_G
VCC33IO
GND
VCCK
GNDK
VCC3IO
I3/PD/S
I3/PD
I3/PD
I3/S
I3/S
I3
O3
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
15
EEPROM Data. EEDIO is the serial output data to EEPROM’s data
input pin and is synchronous with respect to the rising edge of EECK.
EEDIO only drive high / low when access EEPROM otherwise keep at
tri-state and internal pull-up.
Misc. Pins
18
Chip reset input. Active low. This is the external reset source used to
reset this chip. This input feeds to the internal power-on reset circuitry,
which provides the main reset source of this chip.
41
Remote-wakeup trigger from external pin. EXTWAKE_N should be
asserted low for more than 2 cycles of 25MHz clock to be effective.
20
Self_power Indication Input.
0: will respond to Host that this device is a bus-power-device when
Host query device.
1: will respond to Host that this device is a self-power-device when
Host query device.
3
General Purpose Input/ Output Pin 3.
4
General Purpose Input/ Output Pin 2. Please refer to section 2.2.
5
General Purpose Input/ Output Pin 1. Please refer to section 2.2.
6
General Purpose Input/ Output Pin 0 or PME (Power Management
Event). This pin is default as input pin after power-on reset. GPIO_0
also can be defined as PME output to indicate wake up event detected.
7
It is a multi-function pin. The default is an USB Super-speed indicator.
It also can be a GPIO pin. Please refer to Table 2.
8
It is a multi-function pin. The default is an Ethernet PHY LED
indicator (Link 10/100/1000+Active) and programmable details please
refer to Vndcmd. It also can be a GPIO pin.
Please refer to Table 2.
13
It is a multi-function pin. The default is an Ethernet PHY LED
indicator (Link 10/100/1000) and can be a GPIO pin.
Please refer to Table 2.
14
It is a multi-function pin. The default is an Ethernet PHY LED
indicator (Active) and can be a GPIO pin. Please refer to Table 2.
68
Test pin. User can keep this pin NC.
1
Test pin. User can keep this pin NC.
2
Test pin. User can keep this pin NC.
66
Test pin. For normal operation, user should pull down this pin.
67
Test pin. For normal operation, user should pull down this pin.
46
Test pin. For normal operation, user should pull down this pin.
11, 36, 44, Test pin. No connection
51, 52, 64
Power and Ground Pins
25
Analog Power for USB transceiver. 3.3V.
22
Analog Ground for USB transceiver.
26
Analog Power for USB transceiver. 1.2V.
28,30
Analog Ground for USB transceiver.
31
Analog Power for USB transceiver. 1.2V.
33,35
Analog Ground for USB transceiver.
48
Analog Power for Ethernet PHY. 1.2V.
49
Analog Power for Ethernet PHY. 3.3V.
55,61
Analog Power for Ethernet PHY. 1.2V.
58
Analog Power for Ethernet PHY. 3.3V.
37
Digital I/O Power for Clock pins. 3.3V.
40
Digital Ground for clock pins.
10,19,45,65 Digital Core Power. 1.2V.
9
Digital Ground to E-pad
12, 43
Digital I/O Power. 3.3V.
Table 1
: Pinout Description
9
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
2.2 Hardware Setting For Operation Mode and Multi-Function Pins
The following hardware settings define the desired operation mode and some multi-function pins. The logic level shown on
setting pin below is loaded from the chip I/O pins during power on reset based on the setting of the pin’s pulled-up (as logic
‘1’) or pulled-down (as logic ‘0’) resister on the schematic.
EEPROM Offset 05h or eFuse Offset 18h, Flag[4]: Defines the multi-function pin GPIO_0 / PME
GPIO_0 is a general purpose I/O normally controlled by vendor commands. Users can change this pin to operate as a PME
(Power Management Event) for remote wake up purpose. Please refer to Section 4.1.2 “Flag” of bit 4 (PME_PIN).
GPIO_1 pin: Determines whether this chip will go to Default WOL Ready Mode after power on reset. The WOL stands
for Wake-On-LAN.
GPIO_1
0
1
Description
Normal operation mode (default, see Note 1).
Enable Default WOL Ready Mode. Notice that the external pulled-up resistor must be 4.7Kohm.
For more details, please refer to APPENDIX A. Default Wake-On-LAN (WOL) Ready Mode
Note 1: This is the default with internal pulled-down resistor and doesn’t need an external one.
GPIO_2 pin: Determines whether SSTX+ swaps with SSTX- and SSRX+ swaps with SSRX- for USB3.0 PHY.
GPIO_2
0
1
Description
No swapping (default, see Note 1).
Enable swapping. Notice that the external pulled-up resistor must be 4.7Kohm.
MFA_3 ~ MFA_0 pins: There are 4 multi-function pins for LED display purpose and as GPIO controlled by vendor
command PIN Control Register MFA_EN.
PIN Name
Default definition
MFA_3
LED_USB indicator
(Super-speed)
Programmable LED
(Link 10/100/1000+Active)
Programmable LED
(Link 10/100/1000)
Programmable LED
(Active)
MFA_2
MFA_1
MFA_0
Table 2
Section
4.1.6
LED_3
MFA Control Register
MFAIO_3
LED_2
MFAIO_2
LED_1
MFAIO_1
LED_0
MFAIO_0
: MFA_3 ~ MFA_0 pin configuration
10
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
3 Function Description
3.1 USB Core and Interfaces
The USB core and interfaces contains two USB 3.0 transceiver interfaces (PIPE/UTMI) and a USB3.0 Device Controller.
The USB 3.0 transceiver (or PHY) processes USB3.0/2.0/1.1 Physical layer signals. And, The USB3.0 Device Controller is
interfacing with USB 3.0 transceiver by PIPE/UTMI buses and it processes packets of Link layer and protocol layer. Also,
The USB 3.0 Device Controller contains Bulk IN and Bulk OUT buffers for handling Bulk transfer traffic and a FIFO for
Interrupt IN transfers.
The USB core and interfaces are used to communicate with a USB host controller and is compliant with USB specification
V3.0, V2.0, and V1.1.
3.2 Energy Efficient Ethernet (EEE)
It supports IEEE 802.3az also known as Energy Efficient Ethernet (EEE) at 10Mbps, 100Mbps and 1000Mbps. And also
supports EEE specified a negotiation method to enable link partner to determine whether EEE is supported and to select the
best set of parameters common to both device. It provides a protocol to coordinate transitions to/from a lower power
consumption level (Low Power Idle mode) based on link utilization. When no packets are being transmitted, the system
goes to Low Power Idle mode to save power. Once packets need to be transmitted, the system returns to normal mode, and
does this without changing the link status and without dropping/corrupting frames.
To save power, when the system is in Low Power Idle mode, most of the circuits are disabled; however, the transition time
to/from Low Power Idle mode is kept small enough to be transparent to upper layer protocols and applications.
3.3 10/100/1000M Ethernet PHY
The 10/100/1000M Ethernet PHY is compliant with 10Base-T, 100Base-TX, and 1000Base-T IEEE 802.3 standards. It
provides all the necessary physical layer functions to transmit and receive Ethernet packets over CAT 5 UTP cable or CAT
3 UTP (10Mbps only) cable. It uses state-of-the-art DSP technology and an Analog Front End (AFE) to enable high-speed
data transmission and reception over UTP cable. Functions such as Crossover Detection & Auto-Correction, polarity
correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are
implemented.
11
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
3.4 GMAC Core
The MAC core supports IEEE 802.3, IEEE 802.3u and IEEE 802.3ab MAC sub-layer functions, such as basic MAC frame
receive and transmit, CRC checking and generation, filtering, forwarding, flow-control in full-duplex mode, and
collision-detection and handling in half-duplex mode, etc. It supports virtual local area network (VLAN)-tagged frames
according to IEEE 802.1Q specification in both transmit and receive functions, CRC-32 checking at full speed using a
multi-stage, cyclic redundancy code (CRC) calculation architecture with optional forwarding of the frame check sequence
(FCS) field to the user application CRC-32 generation and append on transmit.
3.5 Checksum Offload Engine (COE)
The Checksum Offload Engine (COE) supports IPv4, IPv6, layer 4 (TCP, UDP, ICMP, ICMPv6 and IGMP) header
processing functions and real time checksum calculation in hardware
The COE supports the following features in layer 3:
IP header parsing, including IPv4 and IPv6
IPv6 routing header type 0 supported
IPv4 header checksum check and generation (There is no checksum field in IPv6 header)
Detecting on RX direction for IP packets with error header checksum
The COE supports the following features in layer 4:
TCP and UDP checksum check and generation for non-fragmented packet
TCP Large Send Offload V1
ICMP, ICMPv6 and IGMP message checksum check and generation for non-fragmented packet
3.6 Memory Arbiter
The memory arbiter block is responsible for storing received MAC frames into on-chip SRAM (packet buffer) and then
forwarding it to the USB bus upon request from the USB host via Bulk IN transfer. It also monitors the packet buffer usage
in full-duplex mode for triggering PAUSE frame (or in half-duplex mode to activate Backpressure jam signal) transmission
out on transmit (TX) direction. The memory arbiter block is also responsible for storing MAC frames received from the
USB host via Bulk OUT transfer and scheduling transmission out towards Ethernet network.
12
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
3.7 USB to Ethernet Bridge
The USB to Ethernet bridge block is responsible for converting Ethernet MAC frame into USB packets or vice-versa. This
block supports proprietary burst transfer mechanism (US Patent Approval) to offload software burden and to offer very high
packet transfer throughput over USB bus.
This USB to Ethernet bridge block not only co-work with “eFuse and Control”, “SEEPROM Loader I/F”, and General
Purpose I/Os and LEDs, but also handle USB Control transfers of Endpoint 0.
3.8 eFuse and Control
The eFuse (64-byte) and Control supports user to program USB descriptions and some device information. The data format
is shown at Section 4.
3.9 SEEPROM Loader Interface
The SEEPROM loader interface is responsible for reading configuration data automatically from the external serial
EEPROM or eFuse after power-on reset.
If the content of EEPROM offset 05h (low byte) was equal to (0xFF - SUM [EEPROM offset 03h ~ 04h]), the EEPROM is
the first candidate for SEEEPROM loader. If failed checksum checking the eFuse will be the second candidate.
If this SEEPROM Loader checks the 1st byte data of efuse is not equal to 0xFF and the eFuse Checksum [7:0] of eFuse
offset 19h is correct, the content of eFuse is valid for SEEPROM loader. If eFuse Checksum [7:0] is incorrect, the chip’s
internal default setting will be brought up to configure the corresponding valus and respond to USB standard commands,
etc.
3.10 General Purpose I/O and LED
There are 4 general-purpose I/O pins (named GPIO_0/1/2/3) and 4 multi-function pins group A (named MFA_0/1/2/3)
provided by this chip. The MFA_0/1/2/3 pins are also used for LED indication. Please refer to Section 4.1.6 for details.
13
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
3.11 PLL Clock Generator
The AX88179 integrates internal oscillator circuits for 25 MHz, respectively, which allow the chip to operate cost
effectively with just external 25 MHz crystals.
The external 25 MHz crystal or oscillator, via pins XTL25P/XTL25N, provides the reference clock to internal oscillation
circuit to generate clock source for the embedded Ethernet PHY, embedded USB PHY, and base clock for ASIC use.
The external 25MHz Crystal spec is listed in below table. For more details on crystal timing, please refer to Section 6.5.1
“Clock Timing” and AX88179 demo board reference schematic.
Parameter
Symbol
Typical Value
Fo
25.000000MHz
Nominal Frequency
Oscillation Mode
Frequency Tolerance (@25℃)
Frequency Stability Over Operating
Temperature Range
Equivalent Series Resistance
Load Capacitance
Drive Level
Operation Temperature Range
Aging
Table 3
Fundamental
±30ppm
±30ppm
ESR
CL
70 Ohm max.
12pF
350uW
0℃ ~ +70℃
±3ppm/year
: The external 25MHz Crystal Units specifications
R10 NC,1M
Y1
XTL25P
1
4
2
3
R35
200R
XTL25N
25M CRY STAL
C7
C6
15pF
15pF
Figure 4
: 25MHz Crystal Reference Circuit
14
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
3.12 Reset Generation
The AX88179 integrates an internal power-on-reset circuit, which can simplify the external reset circuitry on PCB design.
The power-on-reset circuit generates a reset pulse to reset chip logic after 1.2V core power ramping up to 0.72V (typical
threshold). The external hardware reset input pin, RESET_N, is fed directly to the input of the power-on-reset circuit and
can also be used as additional hardware reset source to reset the system logic. For more details on RESET_N timing, please
refer to Reset Timing
.
15
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
4 Serial EEPROM/eFuse Memory Map
EEPROM
OFFSET
00h
HIGH BYTE
LOW BYTE
Node ID 1
Node ID 0 (Note_1)
01h
Node ID 3
Node ID 2
02h
Node ID 5
Node ID 4
03h
PID_HB
PID_LB
04h
VID_HB
VID_LB
05h
Flag
EEPROM Checksum (Note_2)
06h
Reserved
Reserved
07h
Max. Power for Self Power
Max. Power for Bus Power
08h
EndPoint1 for SS/HS
EndPoint1 for FS
09h
Language ID High Byte
Language ID Low Byte
0Ah
Length of Product String (bytes)
Offset of Product String (0Eh)
0Bh
Length of Manufacturer String (bytes)
Offset of Manufacturer String (1Ah)
0Ch
Length of Serial Number String (bytes)
Offset of Serial Number String (26h)
0Dh
Length of BOS-type Descriptor (bytes)
Offset of BOS-type Descriptor (2Dh)
19~0Eh
Product String: (Max.) 24 bytes
25~1Ah
Manufacturer String: (Max.) 24 bytes
2C~26h
Serial Number String: (Max.) 14 bytes
3B~2Dh
BOS-type Descriptor: (Max.) 30 bytes
3Ch
Reserved
41~3Dh
42h
Max. Burst: [7:4] for EP3, [3:0] for EP2
Fixed_pattern (10 bytes)
LED_Mode_HB
Table 4
LED_Mode_LB
: Serial EEPROM Memory Map
Note_1: The Node ID 0 value cannot be set to 0xFF and 1st bit of Node ID 0 can not be set to “1” (i.e. cannot be set to
multicast MAC address).
Note_2: The value of EEPROM Checksum field located at EEPROM offset 05h (low byte). The correct value must be equal
to (0xFF - SUM [EEPROM offset 03h ~ 04h]). If SUM [EEPROM offset 03h ~ 04h] has carry, please add ‘1’ to its
result.
Note_3: Total usage is about 134 bytes.
16
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
eFuse
OFFSET
00h
HIGH BYTE
LOW BYTE
Node ID 1
Node ID 0 (Note_1)
01h
Node ID 3
Node ID 2
02h
Node ID 5
Node ID 4
03h
PID_HB
PID_LB
04h
VID_HB
VID_LB
05h
Reserved
Max. Power for Bus Power
06h
EndPoint1 for SS/HS
EndPoint1 for FS
07h
Language ID High Byte
Language ID Low Byte
08h
Length of Product String (bytes)
Offset of Product String (0Bh)
09h
Length of Manufacturer String (bytes)
Offset of Manufacturer String (11h)
0Ah
Length of BOS-type Descriptor (bytes)
Offset of BOS-type Descriptor (16h)
10~0Bh
Product String: (Max.) 12 bytes
15~11h
Manufacturer String: (Max.) 10 bytes
16h
BOS-type Descriptor: (Max.) 2 bytes,
LowByte: SS USB Device Capability bU1DevExitLat,
HighByte: SS USB Device Capability bU2DevExitLat LowByte
Max. Burst, [7:4] for EP3, [3:0] for EP2
BOS-type Descriptor: 1 byte,
SS USB Device Capability bU2DevExitLat HighByte
Flag
Reserved
17h
18h
19h
LED_Mode_LB
1Ah
Fixed_pattern (First byte)
LED_Mode_HB
th
1E~1Bh
1Fh
eFuse Checksum[7:0] (Note_2)
nd
Fixed_pattern (9 ~2 bytes)
Fixed_pattern (10th byte)
Max. Power for Self Power [3:0] and
Reserved [7:4]
Table 5
: eFuse (64-byte) Memory Map
Note_1: The Node ID 0 value cannot be set to 0xFF and 1st bit of Node ID 0 can not be set to “1” (i.e. cannot be set to
multicast MAC address).
Note_2: The correct value of eFuse Checksum field must be equal to (0xFF - SUM [eFuse offset 00h ~ 1Fh excluding eFuse
Checksum field]). If SUM [eFuse offset 00h ~ 1Fh excluding eFuse Checksum field] has carry, please add ‘1’ to its
result.
17
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
4.1 Detailed Description
The following sections provide detailed descriptions for some of the fields in memory maps of serial EEPROM and eFuse.
Please refer to AX88179 EEPROM User Guide for more details.
4.1.1
Node ID (00~02h)
The Node ID 0 to 5 bytes represent the MAC address of the device, for example, if MAC address = 04-23-45-67-89-AB,
then Node ID 0 = 04h, Node ID 1 = 23h, Node ID 2 = 45h, Node ID 3 = 67h, Node ID 4 = 89h, and Node ID 5 = ABh.
Default values: Node ID {0, 1, 2, 3, 4, 5} = 00-0E-C6-81-79-01.
4.1.2
Flag (EEPROM: 05h, eFuse:18h)
Bit 7
PME_IND
Bit 6
PME_TYPE
Bit 5
PME_POL
Bit 4
PME_PIN
Bit 3
SNT
Bit 2
0
Bit 1
WOLLP
Bit 0
RWU
RWU: Remote Wakeup support.
1: Indicate that this device supports Remote Wakeup (default).
0: Not support.
WOLLP: Wake-On-LAN Low Power function.
1: Enabled (default).
0: Disabled.
SNT: Serial Number Type. (Only valid for eFuse)
When SEEPROM loader selected EEPROM:
Please set this bit to ‘0’ for EEPROM. The Serial Number String will refer to Table 4 EEPROM offset 26h ~2Ch.
When SEEPROM loader selected eFuse:
1: Serial Number String is fixed to “00000000000001”.
0: Use Node ID as Serial Number String (default).
For example, when Node ID {0, 1, 2, 3, 4, 5} = 00-0E-C6-81-79-01,
Serial Number String = “00000EC6817901”.
PME_PIN: PME / GPIO_0.
1: Set GPIO_0 pin as PME (default).
0: GPIO_0 pin is controlled by vendor command.
PME_POL: PME pin active Polarity.
1: PME active high (default).
0: PME active low.
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
PME_TYP: PME I/O Type.
1: PME output is a Push-Pull driver (default).
0: PME output to function as an open-drain buffer.
PME_IND: PME indication.
1: A 1.363ms pulse active when detecting wake-up event.
0: A static signal active when detecting wake-up event (default).
4.1.3
Max. Power for Self/Bus Power (07h)
They are Max power values’ setting of powerd device for EEPROM at offset 07h. Bus power setting for eFuse is at
offset 05h (Low Byte), and Self power setting for eFuse at offset 1Fh (High Byte) [3:0].
The default value of Bus Power is 3Eh: For USB 3.0, the power value is 496mA (Unit = 8mA).
For USB 2.0, the power value is 248mA (Unit = 4mA).
Self power setting follows conversion above.
4.1.4
EndPoint1 for SS/HS/FS (EEPROM:08h, eFuse: 06h)
It's Interval (named “bInterval”) for polling Interrupt IN endpoint 1 for data transfers of
Super-Speed/High-Speed/Full-Speed. Expressed in frames or microframes depending on the device operating speed
(i.e. either 1 millisecond or 125 μs units).
(11-1)
The default “bInterval” value is 0Bh for Super-Speed/High-Speed (the polling time of endpoint 1= 2
* 125
μs=128ms) and is 80h for Full-Speed (the polling time of endpoint 1= 128 * 1ms=128ms).
Keep this field as the recommended default values (0Bh for Super-Speed/High-Speed & 80h for Full-Speed).
4.1.5
Max. Burst for EP3/EP2 (EEPROM: 3Ch, eFuse: 17h)
This value is bMaxBurst field in SS endpoint companion descriptor. Refer USB 3.0 spec. 9.6.7.
19
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
4.1.6
LED Mode (EEPROM: 42h, eFuse: 19h~1Ah)
It’s to define the indication setting for LED_0/1/2/3 function of MFA_0/1/2/3 pins.
Bit 7~Bit 0: LED_Mode_LB; Bit 15~Bit 8: LED_Mode_HB
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
LED1_100
LED1_10 LED1_Active LED0_Duplex LED0_1000 LED0_100
LED0_10
LED0_Active
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
1
LED2_Duplex LED2_1000 LED2_100
LED2_10 LED2_Active LED1_Duplex LED1_1000
Note: Bit 15 must be ‘1’ to enable the LED_mode setting; otherwise, it will work at default LED mode.
The LED mode table is as below:
bit
4
Full duplex
0
LED_0
bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
9
Full duplex
0
LED_1
0
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
Link speed(Mbps)
1000
100
10
0
0
0
0
Active
(TX/RX)
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
8
7
6
Link speed(Mbps)
1000
100
10
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
5
Active
(TX/RX)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description of indication
USB3.0 Super Speed: It keeps radiating
when device operated at USB3.0 Super
Speed.
Active (Default for LED_0)
Link 10
Link 10+Active
Link 100
Link 100+Active
Link 100/10
Link 100/10+Active
Link 1000
Link 1000+Active
Link 1000/10
Link 1000/10+Active
Link 1000/100
Link 1000/100+Active
Link 1000/100/10
Link 1000/100/10+Active
Full duplex
Description of indication
USB3.0 Super Speed: It keeps radiating
when device operated at USB3.0 Super
Speed.
Active
Link 10
Link 10+Active
Link 100
Link 100+Active
Link 100/10
Link 100/10+Active
Link 1000
Link 1000+Active
Link 1000/10
Link 1000/10+Active
Link 1000/100
Link 1000/100+Active
20
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
0
0
1
14
Full duplex
bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
4
Full duplex
LED_2
bit
0
1
1
1
1
1
1
0
0
0
13
12
11
Link speed(Mbps)
1000
100
10
0
0
0
0
1
0
10
Active
(TX/RX)
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
3
2
1
Link speed(Mbps)
1000
100
10
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
Active
(TX/RX)
1
LED_3
Table 6
4.1.7
Link 1000/100/10
Link 1000/100/10+Active
Full duplex
Description of indication
USB3.0 Super Speed: It keeps radiating
when device operated at USB3.0 Super
Speed.
Active
Link 10
Link 10+Active
Link 100
Link 100+Active
Link 100/10
Link 100/10+Active
Link 1000
Link 1000+Active
Link 1000/10
Link 1000/10+Active
Link 1000/100
Link 1000/100+Active
Link 1000/100/10
Link 1000/100/10+Active
Full duplex
Description of indication
USB3.0 Super Speed: The LED_0 mode
MUST be set to “Active” only when the
LED_3 is used.
It will radiate when device operated at
USB3.0 super speed and keep flashing
when device is receiving/ transmitting
packets.
: LED Mode Setting Table
Fixed_pattern (EEPROM: 41~3Dh, eFuse: 1F~1Ah)
Please write these 10 bytes of fixed_pattern with hexadecimal (from low bytes to high bytes) = “40 4A 40 00 40 30 0D
49 90 41”.
21
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
4.2 Internal ROM Default Settings
AX88179 supports internal ROM default settings inside chip hardware to enable it to communicate with USB host
controller during enumeration when the AX88179 EEPROM is blank (prior to being programmed) or the value of
EEPROM Checksum field is wrong or the 1st byte data of EEPROM is 0xFF. The default settings inside chip facilitate
users to update the EEPROM content through a Windows PC during R&D validation process or program a blank
EEPROM/eFuse during manufacturing process.
Below table shows AX88179’s internal ROM default settings being used in the case of blank EEPROM or
EEPROM with wrong checksum value or 1st byte data is 0xFF on board. Each of the address offset contains 16-bit data
from left to right representing the low-byte and high-byte, respectively. For example, in offset address 0x01, the ‘C6’ is
low-byte data and the ‘81’ is high-byte data.
Offset
Address
0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
0x40
0x48
0x50
0x58
0x60
0x68
0x70
0x78
0x80~FF
0
8
00 0E
80 0B
31 37
00 00
6F 72
30 30
10 02
00 00
0D 49
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
1
9
C6 81
09 04
39 00
00 00
70 2E
30 30
02 00
00 00
90 41
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
2
A
79 01
0E 07
00 00
41 53
00 00
30 30
00 00
00 00
00 40
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
3
B
90 17
1A 10
00 00
49 58
00 00
30 30
0A 10
00 00
00 80
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
4
C
95 0B
26 0E
00 00
20 45
00 00
30 31
03 00
F3 FF
20 08
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
5
D
B7 73
2D 16
00 00
6C 65
00 00
05 0F
0E 00
40 42
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
Note: The 6 bytes from Internal ROM memory offset 42h to offset 44h are unused.
Table 7
: Internal ROM Memory Map
22
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6
E
00 E0
41 58
00 00
63 2E
30 30
16 00
01 0A
40 00
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
7
F
3E 01
38 38
00 00
20 43
30 30
02 07
FF 07
40 30
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
FF FF
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
4.2.1 Internal ROM Description
The internal ROM is a fixed value. User can’t modify it.
Field Definition
Node ID
Product ID (PID)
Address
Offset
00h ~02h
03h
Vender ID (VID)
Checksum
04h
05h
(Low byte)
Flag - Remote Wakeup 05h
and PME setting, etc.
(High byte)
Max Power for
Bus Power
07h
(Low byte)
Max Power for
Self Power
07h
(High byte)
Length of Product String 0Ah
(High byte)
Length of Manufacturer 0Bh
String
(High byte)
Length of Serial Number 0Ch
String
(High byte)
Product String
0Eh~19h
(Max. 24 bytes)
Manufacture String
1Ah~25h
(Max. 24 bytes)
Serial Number String
26h~2Ch
(Max. 14 bytes)
BOS-type Descriptor
2Dh~3Bh
(Max. 30 bytes)
Default Values
Description
00 0E C6 81 79 01
90 17
Node ID 0 ~ 5
The PID of AX88179 is
0x1790
95 0B
ASIX’s VID is 0x0B95
B7
0xFF - SUM [EEPROM
offset 03h ~ 04h]
73
Enable the “remote
wakeup” and Low Power
WOL function,
(Note 1)
3E
496mA for USB 3.0
248mA for USB 2.0
(Note 2)
01
8mA for USB 3.0
4mA for USB 2.0
(Note 2)
07
Product String Length
(Note 3)
10
Manufacturer String
Length (Note 3)
0E
Serial Number String
Length (Note 3)
41 58 38 38 31 37 39 00 00 00 00 00 00 00 00 “AX88179”
00 00 00 00 00 00 00 00 00
41 53 49 58 20 45 6C 65 63 2E 20 43 6F 72 70 “ASIX Elec. Corp.”
2E 00 00 00 00 00 00 00 00
30 30 30 30 30 30 30 30 30 30 30 30 30 31 “00000000000001”
05 0F 16 00 02
07 10 02 02 00 00 00
0A 10 03 00 0E 00 01 0A FF 07
00 00 00 00 00 00 00 00
Table 8
BOS descriptor
USB 3.0 extension
super speed USB
: Internal ROM Description
23
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Note 1:
Remote Wakeup/PME Settings
The offset 05h field of AX88179 EEPROM is used to configure the Remote Wakeup and PME functions.
Please refer to Section 4 “Serial EEPROM/eFuse Memory Map” for the detailed description of EEPROM offset
05h.
The RWU bit of AX88179 EEPROM offset 05h is used to configure the “bmAttributes” field of Standard
Configuration Descriptor that will be reported to the USB host controller when the GET_DESCRIPTOR
command with CONFIGURATION type is issued. Please refer to below table or “Section 9.6.3 Configuration” of
Universal Serial Bus 3.0 Spec for the detailed description of the “bmAttributes” field of Standard Configuration
Descriptor.
The power mode about Bus-powered or Self-powerd is decided by the SELF_PWR pin when chip powers on.
This will updated to the “bmAttributes” field of Standard Configuration Descriptor.
Note 2: Max Power Setting
The low byte of AX88179 EEPROM offset 07h (for bus-powered) field and high byte of AX88179 EEPROM
offset 07h (for self-powered) field are used to configure the “bMaxPower” field of Standard Configuration
Descriptor that will be reported to the USB host controller when the GET_DESCRIPTOR command with
CONFIGURATION type is issued. Please refer to below table or “Section 9.6.3 Configuration” of Universal
Serial Bus 3.0 Spec for the detailed description of the “bMaxPower” field of Standard Configuration Descriptor.
These fields are used to define the Maximum power consumption of the USB device drawn from the USB bus in
this specific configuration when the device is fully operational.
24
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
Note 3: Product/Manufacturer/Serial Number String Settings
The “Offset” fields of Product/Manufacturer/Serial Number String are fixed in AX88179 EEPROM/eFuse
memory map. Please DON’T change the recommended values of these fields.
If you need to change the Product/Manufacturer/Serial Number strings on your AX88179 EEPROM/eFuse, please
modify the “Length” fields of Product/Manufacturer/Serial Number String to meet the exact string length of your
Product/Manufacturer/Serial Number strings.
4.2.2 External EEPROM Description
User can assign the specific VID/PID, Serial Number, Manufacture String, Product String, etc. user defined fields by
external EEPROM or embedded eFuse. Please refer to AX88179 EEPROM User Guide document for more details
about how to configure AX88179 EEPROM/eFuse content.
Note the EEPROM checksum field should be changed together with the VID/PID fields.
25
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AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
5 USB Configuration Structure
5.1 USB Configuration
The AX88179 supports 1 Configuration.
5.2 USB Interface
The AX88179 supports 1 interface.
5.3 USB Endpoints
The AX88179 supports following 4 endpoints:
Endpoint 0: Control endpoint. It is used for configuring the device.
Endpoint 1: Interrupt endpoint. It is used for reporting network Link status.
Endpoint 2: Bulk IN endpoint. It is used for receiving Ethernet Packet.
Endpoint 3: Bulk OUT endpoint. It is used for transmitting Ethernet Packet.
26
Copyright © 2011-2014 ASIX Electronics Corporation. All rights reserved.
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6 Electrical Specifications
6.1 DC Characteristics
6.1.1 Absolute Maximum Ratings
Symbol
VCCK
VCC12A_TX
VCC12A_RX
VCC12A_X
VCC12A
VCC3IO
VCC33IO
VCC33A
VCC33A_X
VCC33A_G
VIN3
TSTG
IIN
IOUT
Parameter
Digital core power supply
Analog Power for USB Transceiver. 1.2V
Analog Power for USB Transceiver. 1.2V
Analog Power for Ethernet PHY. 1.2V
Analog Power for Ethernet PHY.1.2V
Power supply of 3.3V I/O
Power supply of 3.3V for clock pin.
Analog Power 3.3V for USB Transceiver.
Analog Power for Ethernet PHY. 3.3V
Analog Power for Ethernet PHY. 3.3V
Input voltage of 3.3V I/O
Input voltage of 3.3V I/O with 5V tolerant
Storage temperature
DC input current
Output short circuit current
Rating
- 0.5 to 1.44
- 0.5 to 1.6
- 0.5 to 1.6
- 0.1 to 1.26
- 0.1 to 1.26
- 0.5 to 4.2
- 0.5 to 4.6
- 0.5 to 4.6
- 0.4 to 3.7
- 0.4 to 3.7
- 0.5 to 4.2
- 0.5 to 5.8
- 65 to 150
50
50
Unit
V
V
V
V
V
V
V
V
V
V
V
V
℃
mA
mA
Note: 1.Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be
restricted to the optional sections of this datasheet. Exposure to absolute maximum rating condition for extended
periods may affect device reliability.
2. The input and output negative voltage ratings may be exceeded if the input and output currents under ratings are
observed.
6.1.2 Recommended Operating Condition
Symbol
VCCK
VCC12A_TX
VCC12A_RX
VCC12A_X
VCC12A
VCC3IO
VCC33IO
VCC33A
VCC33A_X
VCC33A_G
VIN3
Tj
Ta
Parameter
Digital core power supply
Analog Power for USB Transceiver. 1.2V
Analog Power for USB Transceiver. 1.2V
Analog Power for Ethernet PHY. 1.2V
Analog Power for Ethernet PHY.1.2V
Power supply of 3.3V I/O
Power supply of 3.3V for clock pin.
Analog Power 3.3V for USB Transceiver.
Analog Power for Ethernet PHY. 3.3V
Analog Power for Ethernet PHY. 3.3V
Input voltage of 3.3 V I/O
Input voltage of 3.3 V I/O with 5V tolerance
Maximum junction operating temperature
Ambient operating temperature
Min
1.14
1.14
1.14
1.14
1.14
3.13
3.13
3.13
2.97
2.97
3.13
3.13
0
Typ
1.2
1.2
1.2
1.2
1.2
3.3
3.3
3.3
3.3
3.3
3.3
3.3
-
Max
1.26
1.26
1.26
1.26
1.26
3.47
3.47
3.47
3.63
3.63
3.47
5.25
125
70
27
Copyright © 2011-2014 ASIX Electronics Corporation. All rights reserved.
Unit
V
V
V
V
V
V
V
V
V
V
V
V
℃
℃
AX88179
USB 3.0 to 10/100/1000M Gigabit Ethernet Controller
6.1.3 Leakage Current and Capacitance
Symbol
IIN
Parameter
True 3.3 V I/O input leakage
current
Conditions
Vin = 3.3 V or 0 V
Min
-
Typ
≤±1
Max
-
Unit
μA
3.3 V with 5 V tolerance I/O
Vin = 5 V or 0 V
-
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